The present invention relates to a data transfer controlling device for performing a data transfer between a memory and a peripheral device in a direct memory access (hereinafter referred to as "DMA") system.
In many cases, an information processing system using a microcomputer transfers a large amount of data between a peripheral device and a memory, processes the data by a central processing unit (CPU) and further transfers the processed data to another peripheral device and memory. For example, in a print control/processing system, a CPU receives data from a host computer, processes the received data and transfers the processed data to a printing device at the rate of the data of one character in response to one transfer request from the printing device. In this case, if the above data transfer is executed in an interruption routine in accordance with an interruption request from a peripheral device (e.g., printing device) to the CPU, overhead (time taken for the interruption processing) of the CPU will increase thereby to reduce the efficiency of data processing in the system. In order to obviate such inconvenience, a direct memory access controller (hereinafter referred to as "DMAC") has been proposed as a data transfer controlling device dedicated to controlling the data transfer.
The data transfer using DMAC (hereinafter referred to as "DMA transfer") is carried out as follows. First, several kinds of items of information such as a memory address for which the data transfer is to be made and the number of DMA transfers are previously set in DMAC by means of an instruction execution by CPU. When DMAC detects a request of DMA transfer sent from a peripheral device such as a printing device and a display device, it requests CPU for the privilege of using a bus. When CPU detects this request, it delivers the privilege of using the bus including an address bus and a data bus to DMAC. Using the delivered bus, DMAC produces an item of address information and a read/write signal to transfer the data stored in a memory to the peripheral device which requested the DMA transfer.
Thereafter, the requested number of DMA transfers (e.g., corresponding one character to be printed) will be repeated. When such data transfer is completed, DMAC informs the CPU of completion of the DMA transfer requested. When CPU detects the completion of the DMA transfer, it executes an interruption processing and an interruption processing program routine. In the interruption processing program routine, CPU resets several kinds of control information for DMAC for preparation of the subsequent DMA transfer. Thus, the DMA transfer will be carried out again.
Now, referring to the drawings, explanation will be given of data transfer from a memory to a peripheral device using the conventional DMAC.
FIG. 1 is a block diagram showing the main part of a conventional information processing system 500.
The information processing system 500 is composed of a microcomputer 501 including a CPU 511 and a DMAC 512, a memory 503 and a peripheral device 502.
CPU 511 incorporates a program counter (PC), a program status word (PSW), several kinds of registers. Using them, CPU 511 controls the operation of the entire information processing system 500, including controlling the execution of several kinds of instructions, and controlling the privilege of using a bus 505 through which an address signal, data, and a read/right signal are passed.
DMAC 512 is composed of at least one set of a memory address register (MAR) 513 for storing the address information to be subjected to the DMA transfer, a terminal counter (TC) 514 for storing the number of data to be transferred and a terminal counter modulo register (TCM) 515 for storing an initial value of the number of data to be transferred. Prior to starting the DMA transfer, CPU 511 previously sets in MAR 513 the address for which the DMA transfer is to be started and sets in TC 514 and TCM 515 the number of data to be transferred in response to each DMA transfer request made. When DMAC 512 detects the signal 520 of requesting the DMA transfer supplied from the peripheral device 502, it acquires the privilege of using the bus 505 from CPU 511 through an exchange of a bus hold requesting signal (HLDRQ) which requests CPU to hold the privilege of using the bus 505 and a hold acknowledge signal (HLDAK) which permits DMAC 512 to use the bus 505, and then executes the DMA transfer between the memory 503 and the peripheral device 502.
Memory 503 is composed of a program region for CPU 511, a data area, a DMA transfer source region A 530 and a DMA transfer source region B 531, and stores, under the control by CPU 511 or DMAC 512, several kinds of data for the information processing system 500 through the bus 505 through which an address signal, data and a read/write signal are passed. In operation, prior to starting the DMA transfer, CPU 511 writes the data to be DMA-transferred in the DMA transfer source region A 530. Upon completion of write of final data in the DMA transfer source region A 530, CPU 511 permits executing the DMA transfer for the DMA transfer source region A 530. Then, DMAC 512 burst-transfers (or collectively transfers) the data stored in the DMA transfer source region A 530 to the peripheral device 502. It should be noted that during the period other than execution of the DMA transfer for the DMA transfer source region A 530, CPU 511 writes the DMA-transfer data in the DMA transfer source region B 531. After DMAC 512 completes the DMA transfer to the final data for the source region A 530, it will execute the DMA transfer in the source region B 531 if the data to the final data have been stored in the region B 531. Thus, the DMA transfer source regions A 530 and B 531 will be alternately subjected to the DMA transfer by DMAC 512 or the storage by CPU 511.
Detailed explanation will be given of the DMA transfer operation between the memory 503 and the peripheral device 502.
When the necessity arises for the peripheral device 502 to receive the data to be DMA-transferred corresponding to the number of times set in TC 514, the peripheral device 502 activates the DMA transfer requesting signal 520 to supply it to DMAC 512. In response to activation of the DMA transfer requesting signal 520, DMAC 512 activates the HLDRQ signal 522 to require CPU 511 to hold the privilege of using the bus 505.
Meanwhile, CPU 511 executes a predetermined program processing including creating data and storing the created data in the DMA transfer source region A 530 and also always monitors the status of the HLDRQ signal 522 supplied from DMAC 512. Now, when CPU 511 detects activation of the HLDRQ signal 522, with the contents of PC, PSW and several kinds of registers being held at their values during program execution, it activates the HLDAK signal 523 to inform DMAC 512 of having given the bus using privilege.
DMAC 512 which has acquired the bus using privilege sends the address information for the DMA transfer in the DMA transfer source region A 530 to the bus (address bus) 505, and also activates the memory read signal to send the transferred data onto the bus 505. Subsequently, DMAC 512 activates the memory write signal (or DMA acknowledge signal) 521 to write the DMA-transferred data in the peripheral device 502.
Each time the DMA transfer has been made, the content of the memory address register MAR 513 is updated, and the content of the terminal counter TC 514 which stores the number of transfer data is decremented by "1". DMAC 512 repeats the above DMA transfer. When DMAC 512 completes the DMA transfer by the predetermined number of times (the content of TC 514 has been decremented to "0"), it makes the HLDRQ signal 522 inactive so as to inform CPU 511 of aborting the bus using privilege. Thus, CPU 511 takes back the bus using privilege and resumes the program execution. Further, DMAC 512 presets the value of the terminal counter modulo register TCM 515 into the terminal counter TC 514 to initialize TC 514 in preparation for the subsequent request of the DMA transfer, and activates a DMA interruption requesting signal 524 to inform CPU 511 of the completion of the DMA transfer.
When CPU 511 receives the signal 524 from DMAC 512, it saves PC and PSW toward a stack area, and starts the interruption processing program routine. In this program routine, for example, as seen from the flowchart of FIG. 3, in order to prevent the data stored in the memory region other than the DMA transfer source regions from being DMA-transferred, the number of interruptions that have occurred (the number of times when TC has been decremented to "0") is counted. And, when the number of times becomes a predetermined value, a decision that the data transfer has been carried out to the final data in the DMA transfer source regions is made. On the basis of this decision, the DMA transfer is inhibited by resetting a transfer permission bit, for example. Further, the DMA transfer starting address of the DMA transfer source region B 531 is set in MAR 513. If, at this time, writing the data to be transferred to its final data in the DMA transfer source region B 531 has been completed by CPU 511, the process of permitting the DMA transfer for the source region B 531 is made. Upon completion of executing the interruption processing routine, CPU 511 recovers PC and PSW from the stack area.
The information processing system using the prior art DMA transfer controlling method and apparatus hitherto explained has the following defects.
As seen from FIG. 4, upon completion of a predetermined number of times of the DMA transfer in the above information processing system, CPU 511 executes an interruption process of saving PS and PSW to a stack region and recovering them therefrom, and also an interruption program process such as examining if the DMA transfer for the DMA transfer source region has been completed to its final data and if completed, inhibiting the DMA transfer ( 1 in FIG. 4). While the interruption process and the interruption program process are being executed, DMAC 512 must hold the DMA transfer request issued from the peripheral device ( 3 in FIG. 4). Specifically, the DMA transfer request must be held for a long time (the time required to respond to the DMA transfer request) from the issuance of the request to the actual execution of the DMA transfer. Further, CPU deals with the process relating to the DMA transfer for a long time, so that it cannot execute the inherent process at a high speed. Particularly, this is remarkable in a print control process system. Namely, in this system, the number of times of transfer responding to each DMA transfer request can be set for the number of bytes corresponding to one character data to be printed (3 bytes if one character is composed of 24.times.24 dots). Thus, the DMA transfer interruption process must be executed very frequently.
Further, upon completion of the DMA transfer to the final data for the DMA transfer source area, CPU inhibits the DMA transfer and this inhibition is done within the interruption process. Therefore, if the subsequent DMA transfer request is issued during the period until the inhibiting time ( 4 in FIG. 4), DMAC will DMA-transfer the data existing in the memory region other than the DMA transfer source areas.